That was some night of celebration! Now past the ebbing wave of our once-blissful incognizance, we are become increasingly aware that the fireworks display back there did not herald the onset of any newfound freedom — rather a lonely trudge back to the drawing board in the very near future, accompanied only by the growing realization that a) switching power conversion is not half as easy as it sounds, and b) reliability should never be considered to be a flash in the pan.

In the previous month's column we revealed that many integrated switcher ICs are virtually indestructible by design. In that case, why even bother about knowing all about the peak currents? To answer this delicately and with a measure of natural human kindness — the second current limit not only helps make the IC 'bulletproof', but also 'idiot-proof'. This second current limit, if present, is not even supposed to be encountered under normal operation, or even under even under “normal abnormal conditions”! That sounds oxymoronic, but in fact most of us practicing engineers would have to struggle extremely hard to even get the peak current to slip past the first current limit unnoticed, so as to trigger the IC into this last-ditch survival mode. But if that happens, unfortunately now the problem is that the converter output just folds back (low output voltage at higher loads). This in turn is the result of the second level current limit comparator being designed to either cause a smooth, progressive reduction in the switching frequency ('frequency foldback'), or just skipping several on-pulses (the number of pulses skipped being roughly proportional to the amount by which the peak current is exceeding the second level threshold — an averaged kind of frequency foldback).

But before looking further at frequency foldback, let us again beat upon some of the points from the previous month's column, and refine them further. We saw that for a low-voltage integrated switcher, we can for example use a “5A device” for a 3A load — and then its OK to use only a 3A inductor. Note that we have been talking only about buck switchers so far. A “5A” buck switcher is by definition meant for a maximum load current ('Io') of 5A, and therefore its current limit ('Iclim') will usually always be internally set a little higher, maybe between 6 to 6.5A. But this train of logic relies on a property that is specific only to the buck topology:- its average inductor current equals its load current. We also recollect that the usual design procedure for selecting the inductance for any dc-dc topology is to set the peak inductor current about 20% higher than the average inductor current. We can show that this '20% inductor criterion' leads to an 'optimum' of sorts from the viewpoint of all the power components of the converter (for more details see application note AN-1197). So for a buck, with a 5A load current, we will typically have a peak inductor current of 5 x (1 +0.2) = 6A. But remember, this holds only for a buck!

For 'non-buck' topologies we have to be careful because there *the load current has no simple relationship to the average inductor current.* And therefore nor to its peak either, and nor to the required current limit. This means that if we come across a device declared to be say a “5A buck-boost” (or boost) switcher IC, we should remember that this just means that 5A is its set *current limit, NOT its max load current* . The max load for a non-buck topology depends on the input-output conditions of the particular application. For the boost and the buck-boost, the average inductor current is not the load current 'Io' but is Io divided by (1-D), where D is the duty cycle. (SeeAN-1246 for more details). This leads to the following basic design rule for the two 'non-buck' topologies: *the worst-case average (and peak) inductor current occurs at the lowest input voltage* . That is thus the input end at which we must design or select our inductor. In contrast, for a buck, we always pick its inductance at the maximum input voltage of the application, because that is the end at which its peak current is the maximum.

We need to refine the above numerical computations slightly and to also see the *importance of tolerances in reliability and cost* . We said that for a low-voltage 5A buck we can pick a 3A rated inductor if our max load current is 3A. That is not completely accurate. Though the chosen inductor is allowed to have a 3A continuous rating (based on the copper thickness and core loss), its peak or saturation rating (i.e. the current at which the core shouldn't saturate even momentarily) must be such that it can handle the peak current, which by design is typically about 20% higher than the average value i.e. 3 x 1.2 = 3.6A. But we also know that if this happens to be a “high voltage” application (defined here as an input greater than about 40V) we may have to size our inductor according to the current limit, not the load current. That number is 5A in this case. But very roughly so!

Here we should actually check the IC datasheet to see the MAX value of the current limit range. For example, for a 5A switcher the MIN value may be say 6A (set high enough simply to guarantee full 5A load capability with the usual 20% inductor design criterion mentioned above), but the MAX value of the current limit may be say 7A over temperature and process variations, and depending upon how it may have been trimmed in production. So now, though the inductor needs to have a minimum continuous rating of only 3A (for a load current of 3A), the inductor must be able to handle peaks of 7A! That primarily determines the size and cost of the inductor. Not the amount of copper. In fact, for a high voltage application, the load current is not really important anymore, because the weight of copper used doesn't really affect the inductor cost much, provided of course that the available winding window area is enough to accommodate the required number of turns, and so we are not being forced to pick a larger core size simply to accommodate the required windings, or because the overall core temperature is too high as a result of excessively thin wire gauge.

We also now realize that all “5A” switchers from different vendors are not necessarily the same! The *spread/tolerance of the current limit* is very important as it determines the size and cost of the inductor when dealing with high voltage ICs. The MIN value of the current limit is important because it determines the minimum guaranteed power output, and the MAX value of the current limit determines the size of the inductor. Therefore, some key manufacturers of high voltage integrated circuits pride themselves on how 'tight' their tolerance is on the set current limit. That is indeed admirable, but only provided we are comparing apples to apples; that is, comparing only high voltage integrated switcher families with fixed current limits from different vendors. This comparison makes no sense if we have a device (e.g., a controller) where we can set the current limit externally. In that case we can match the current limit much more accurately to the load current, and thus get the smallest possible core size. That helps reducing core size. (More on this aspect in the next month's column and how such vendors virtually trick us into 'thinking' that the core size has decreased.)

For non-buck topologies, we now realize that say for a buck-boost application with an input of 15V to 25V and an output of “15V output, the max duty cycle is 50% and this occurs at the minimum input of Vin = 15V. So if the load current is 5A, the average inductor current is 5/(1-0.5) = 10A. With the 20% inductor criterion, the peak switch current will be 10 x 1.2 = 12A. So the MIN of the current limit must be set higher than 12A. And then depending on the available accuracy for current limit, the MAX may be as high as say 20A. Clearly, a 5A switcher is not going to suffice, nor an inductor rated only for 5A!

A related issue is the case when a buck IC is used in a so-called 'inverting configuration'. We should realize that in doing so actually the topology has in effect *changed from a buck to a buck-boost* . So now we just cannot get 5A of load current from a declared '5A' IC. How much load current is possible depends on the specific input-output conditions. So again, nor is our peak current in the presumed 5A ballpark, and nor should our inductor rating be. Or we will certainly be frozen into a July 4th timeframe forever.

From an IC designer's point of view and even our applications level understanding; we must carefully recognize another basic problem with the very concept of current limit. Suppose we now have a very 'fast acting' current limit, and we also use 'blazingly fast' FETs (very low gate charge). Does that mean we are 100% protected? Not necessarily! What does the current limit comparator really do? All it can do is to command the duty cycle to reduce further when we hit the current limit. But it can't make the pulse width narrower than a certain *minimum on-time* . This small minimum pulse width of about 100-150ns is usually required for the internal circuitry to be able to sense the current every cycle, and we also actually have to turn the switch ON every cycle for the purpose. In fact this minimum pulse width may need to be set even higher, say around 150-250ns, especially if we are using controllers (as opposed to integrated switchers) since a 'good' controller IC must handle a relatively wide range of FET characteristics, and various possible PCB layouts and their corresponding trace delays and glitches.

Current mode control may also be worse-off in this regard, because of the need to incorporate a certain higher than usual minimum leading edge noise blanking time. Generally, high frequencies will aggravate the situation further, since the same minimum pulse width corresponds to a much higher minimum duty cycle at high frequencies. What this leads to is the very curious situation as indicated in the accompanying figure (for a buck). Consider a 'hard' power-up i.e. a sudden application of input power, with a high dV/dt, as say with a banana plug slammed into the lab dc power supply. Initially, there is no output voltage rail present, so the current ramps up at the rate of Vin/L, eventually steadying to (Vin-Vo)/L. But during the off-time, at initial powerup, the ramp-down rate is much smaller, as it depends basically only on the diode voltage drop of 0.5 Volts or so. So every cycle, the net current rises just a little higher, irrespective of any current limit. This is a clear case of current staircasing. Over several cycles, depending on the amount of output capacitance and the input dV/dt, the inrush current may go up to very high and almost unpredictable levels. Even 'soft-start', if available, may serve absolutely no purpose at all, at least not in controlling the inrush current. The situation actually gets worse with a 'good' diode i.e. one where the diode voltage drop is less, because it is this diode drop that stands almost alone in trying to get the current to ramp down. The same thing happens if we short the output!

One solution to this problem is to reduce the frequency (or just omit on-pulses as shown the lower diagram of the figure). This effectively increases the off-time and reduces the minimum duty cycle, and thus gives enough time for the current to ramp down. See the datasheet for LM1572 for a deeper explanation of such a practical frequency foldback scheme. But note that if too much off-time is available (an excessive amount of frequency foldback), the average current may not be able to rise high enough to meet even the initial load requirement under startup. That could well lead to a scenario that is rather uncomfortably well known in the semiconductor industry — that of an IC which has a declared and mysterious “startup problem” under certain types of loads. In general, we have to be very careful in implementing any type of foldback scheme. Foldback is a two-edged sword. It might help control responses to abnormal conditions, but may also end up encroaching on normal responses.

Another method being used nowadays for synchronous buck ICs is to sense the current during the off-time (i.e. across the lower FET). Note that this allows us to skip on-pulses entirely and is in effect is a frequency foldback of sorts. Though its main purpose in powering modern core processors is to be able to carry out a high-to-low conversion at high switching frequency. For example, from 20V to 1V at 1MHz would require 1/20th of 1us i.e. an on-pulse no wider than 50ns. That doesn't leave us much time to be able to sense current in the high-side FET. So the only option is to sense current in the low-side FET. On the face of, low-side sensing should also help restrict the current under startup and overloads. But it has its own set of peak current and reliability problems, and these will form the subject of a column in the near future.

**Sensing the current during the off-time allows us to skip on-pulses entirely and is in effect is a frequency foldback**

Write me at sanjaya.maniktala@nsc.com. Please don't hesitate to ask for pdfs of my older articles, as some of you have already done. And also don't forget to also write Steve (at sohr@cmp.com) and give us the good news that the fireworks display is over at your end.

*Editor's Note: Sanjaya has a new book out, which the publisher, McGraw-Hill Professional is promoting as “The Bible” for power supply designers. On, Amazon.com, the title is Switching Power Supply Design & Optimization
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